It is often desired in an integrated circuit to delay a signal. In the context of a periodic signal like a clock signal, adjustment of delay can be understood as an adjustment of the phase of the signal. Such phase shifting of a clock signal can be achieved by use of a delay locked loop (DLL), which is commonly used to generate internal clock signals for an integrated circuit from a master external clock signal. Because of the complexity of modern-day integrated circuits, the ability to finely shift the phase of clock signal is particularly important to ensure proper timing and synchronization within the circuit.
A typical DLL 10 is shown in FIG. 1. As shown, the DLL 10 derives an (internal) output clock signal (ClkOut) (or more than one output clock signal; only one is shown for simplicity) from an (external) input clock signal (ClkIn), in which the phase or delay between the two clocks can be tightly controlled. The DLL 10 comprises a variable delay line (VDL) 12 for providing a variable amount of delay to the input clock signal, and a delay module (DM) 14 for providing a fixed delay to the input clock signal. The output of the DM 14 (essentially, a representation of the output clock) and the input clock signal, ClkIn, are compared at a phase detector (PD) 16, which essentially determines whether one of these signals is lagging or leading the other, and seeks to bring these two phases into alignment. For example, if the output of the DM 14 leads ClkIn, then the phase detector outputs an “Up” signal, which increases the delay through the VDL 12. By contrast, if the output of the DM 14 lags ClkIn, then the phase detectors outputs a “Down” signal to decrease the delay through the VDL 12. Through this scheme, the output clock signal, ClkOut, is locked into a phase relationship with the input clock signal, ClkIn.
One example of a variable delay line (VDL 12) is shown in FIG. 2. As mentioned above, the VDL 12 receives control signals “Up” or “Down” from the phase detector 16 to control the amount of delay that VDL 12 imparts to the input clock signal, ClkIn. In this regard, the exemplary VDL 12 is comprised of a plurality of stages 20a-d. Four such stages 20 are shown in FIG. 2 for simplicity, but a realistic VDL 12 would normally have tens of stages. Each stage 20 in this example comprises a D flip flop 22 and a few NAND gates. The control signals “Up” and “Down” from the phase detector 16 adjust at which stage 20 the ClkIn signal will enter the VDL 12, which in turn defines the delay the VDL imparts. For example, as shown, the “Up”/“Down” control signals have been used to set stage 20c as the entry point for ClkIn. Accordingly, the outputs Q/Q* of flip flop 22c have been set to 1/0, while all other flip flops 22a, 22b, and 22d have their outputs set to 0/1. As these logic signals percolate through the NAND gates as shown, it can be seen that ClkIn will pass through the NAND gates only in entry stage 20c and all subsequent stages (i.e., 20d), and the inherent delays in those NAND gates will function to delay the signal.
Should the phase detector 16 determine that the delay needs adjustment, one of control signals “Up” or “Down” would be asserted. For example, assume from the initial condition in FIG. 2 that an “Up” signal is subsequently asserted, because the phase detector has decided that further delay is warranted in the VDL 12. This would shift the asserted flip flop 22 output Q/Q* of 1/0 to the next stage to the left, i.e., to flip flop 22b, with all other flip flop outputs set to 0/1. As a result, the ClkIn signal would now enter the VDL at stage 20b, and hence would pass through the NAND gates in stages 20b, 20c, and 20d, thus increasing the delay through the VDL 12. By contrast, a “Down” signal would shift the entry point one stage 20 to the right, decreasing the delay through the VDL 12. In other embodiments, the control signals “Up” and “Down” could be combined for example, and thus only one control signal is necessary to control the VDL 12 in many useful embodiments, although two digital control signals are shown in FIG. 1.
It is typical to provide the circuit elements in the VDL 12 (the flip flops 22, the NAND gates, etc.) with a dedicated power supply voltage node (VccVDL) which is isolated from the master power supply voltage (Vcc) of the integrated circuit, as is shown in block diagram form in FIG. 1. Providing an isolated power supply to the VDL 12 is beneficial to prevent perturbations in the master power supply Vcc from being seen by the VDL 12 and adversely affecting its delay. Such isolation is important: without isolation, if the VccVDL node becomes higher than normal because of perturbations present on Vcc, delay through the VDL 12 will be quicker than expected, because a higher power supply voltage will cause the circuit elements in the VDL 12 to act more quickly. Conversely, if VccVDL node becomes lower than normal, the opposite occurs, and delay through the VDL 12 will be slower than expected.
To isolate these two power supplies, and as shown in FIG. 1, VccVDL is generated from the master power supply Vcc using a voltage regulator circuit 15. The details of such a regulator circuit 15 are variant and well known, and hence are not shown for simplicity. While VccVDL is shown as comprising an isolated power supply dedicated only to the VDL circuitry, one skilled in the art will realize that this isolated power supply may be used to power other subcircuits in the integrated circuit as well, depending on the designer's preferences and subject to the noise tolerance of the VDL 12.
While the regulator 15 may protect the VDL 12 from power supply voltage variations which could effect its delay, the VDL 12 still remains subject to variations in delay due to temperature. Such variation is illustrated in FIG. 6A. Shown are the results of a computer simulation that models the output of the VDL 12 (ClkOut) versus its input (ClkIn, set to 100 MHz in the simulation). As can be seen, the delay imparted by the VDL 12 varies significantly with temperature. When the delays at 0 degrees Celsius (0 C) and 100 degrees Celsius (100 C) are simulated through some set number of stages 20 (FIG. 2), it is seen that a difference of approximately 220 picoseconds exists in the delays at these two temperature extremes. Obviously, this is not ideal: the delay through the VDL 12 is preferably not dependent on the vagaries of temperature, but instead is preferably only affected by the phase detector 16 control signals, “Up” and “Down.”
In the context of a DLL circuit 10, such temperature variations, and resulting delay variations in delay through the VDL, are in theory addressed and remedied via the feedback loop that the DLL provides. However, because of the feedback nature of the DLL 10, the DLL cannot remediate itself immediately: it can take some time for the output (ClkOut) to reflect modification in the VDL 12 as necessitated by temperature changes. Moreover, depending on the loop filter characteristics of the DLL's feedback path, changes in the output (ClkOut) warranted by temperature changes could become unstable and resonate. Such effects can become more pronounced when the integrated circuit switches between modes which vary in their power consumption, and thus cause sharp variations in temperature. In a Synchronous Dynamic Random Access Memory (SDRAM) for example, switching between normal and self-refresh modes of operation provides a good example of a mode switch which can affect integrated circuit temperatures and therefore DLL performance.
In short, when the feedback nature of the DLL 10 is used to compensate for the effects of temperature on the VDL 12, jitter can result in the output of the DLL, meaning that the phase of the output can vary significantly from the locked phase condition the DLL seeks to establish. Such jitter is obviously undesirable, especially when it is considered that temperature-related jitter at its worst case can take on the order of at least a period of a clock cycle before being compensated for.
Moreover, even outside the context of DLLs, FIG. 6A should be understood as illustrative concerning the effects of temperature on delay elements generally. Although FIG. 6A illustrates the effects of temperature on the delay of a VDL 12, the fact remains that other types of delay elements would also behave similarly: at higher temperatures, the delays would be inherently longer than at lower temperatures. Delay elements are used in all sorts of circuitry in an integrated circuit, and in many applications it would be highly desirable that the delays they produce not be dependent on temperature.
The solutions described in this disclosure address the above-mentioned problems.